Compile once, run everywhere!

RV-VEP (RISC-V Virtualized Embedded Platform) is a universal binary platform for embedded systems. We work to make a uniform ecosystem of embedded software possible by abstracting out differences in instruction sets and SoC specs.

Why not WebAssembly?


RV-VC (RISC-V Virtualizable Code) is our customized instruction set based on RISC-V. We add metadata and extended instructions based on RV32IM.

RV-VC is a platform-independent intermediate representation of programs and is not executed directly by hardware. Instead, just before flashing to the device another compilation is done to produce code suitable for running on the target architecture.


RV-VRT (RISC-V Virtualized Runtime) is an operating system that manages execution of RV-VC code. It needs to:

  • Resolve dependencies and perform dynamic linking on RV-VC modules.
  • Provide a URL-based uniform resource registration and lookup service.
  • Provide an abstraction layer for external devices and interrupts.
  • etc.


Task 1: LLVM backend for RV-VC

Below shows the compilation pipeline of RV-VEP:

Compile Pipeline

The last step here is to compile RV-VC for the target hardware. To enable fully static (AoT) compilation we need some metadata from the previous step, more specifically, indirect branch hints.

Task 2: An AoT compiler for generating Thumb2 from RV-VC

Cortex-M is the most widely used microcontroller core in the industry and uses the Thumb2 instruction set. So implementing a RV-VC to Thumb2 compiler ensures that RV-VC runs on the mostly-used series of embedded SoC.

We suggest to implement an LLVM-based compiler so that porting to other platforms would be easy, but you can also write a direct binary translator :)

Task 3: RV-VRT operating system

To provide a consistent development experience across platforms, RV-VEP needs more than a universal binary format. Similar to WASI in the WebAssembly ecosystem, RV-VEP also requires a consistent module interface and hardware interface and that's what we aim to do with RV-VRT.